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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>MOV (from general) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">MOV (from general)</h2>
      <p class="aml">Move general-purpose register to a vector element. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&amp;FP register.</p>
      <p class="aml">This instruction can insert data into individual elements within a SIMD&amp;FP register without clearing the remaining bits to zero.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    <p>
        This is an alias of
        <a href="ins_advsimd_gen.html">INS (general)</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="ins_advsimd_gen.html">INS (general)</a>.
        </li><li>The description of <a href="ins_advsimd_gen.html">INS (general)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td colspan="5" class="lr">imm5</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="MOV_INS_asimdins_IR_r"/><p class="asm-code">MOV  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;imm5&quot;) [B,D,H,S]">&lt;Ts&gt;</a>[<a href="#sa_index" title="Element index (field &quot;imm5&quot;)">&lt;index&gt;</a>], <a href="#sa_r" title="Width specifier for general-purpose source register (field &quot;imm5&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_n" title="General-purpose source register number [0-30] or ZR (31) (field &quot;Rn&quot;)">&lt;n&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="ins_advsimd_gen.html#INS_asimdins_IR_r">INS</a>  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;imm5&quot;) [B,D,H,S]">&lt;Ts&gt;</a>[<a href="#sa_index" title="Element index (field &quot;imm5&quot;)">&lt;index&gt;</a>], <a href="#sa_r" title="Width specifier for general-purpose source register (field &quot;imm5&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_n" title="General-purpose source register number [0-30] or ZR (31) (field &quot;Rn&quot;)">&lt;n&gt;</a></p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ts&gt;</td><td><a id="sa_ts"/>
        <p>Is an element size specifier, 
      encoded in
      <q>imm5</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">imm5</th>
                <th class="symbol">&lt;Ts&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">x0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">xxxx1</td>
                <td class="symbol">B</td>
              </tr>
              <tr>
                <td class="bitfield">xxx10</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">xx100</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">x1000</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;index&gt;</td><td><a id="sa_index"/>
        <p>Is the element index 
      encoded in
      <q>imm5</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">imm5</th>
                <th class="symbol">&lt;index&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">x0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">xxxx1</td>
                <td class="symbol">imm5&lt;4:1&gt;</td>
              </tr>
              <tr>
                <td class="bitfield">xxx10</td>
                <td class="symbol">imm5&lt;4:2&gt;</td>
              </tr>
              <tr>
                <td class="bitfield">xx100</td>
                <td class="symbol">imm5&lt;4:3&gt;</td>
              </tr>
              <tr>
                <td class="bitfield">x1000</td>
                <td class="symbol">imm5&lt;4&gt;</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;R&gt;</td><td><a id="sa_r"/>
        <p>Is the width specifier for the general-purpose source register, 
      encoded in
      <q>imm5</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">imm5</th>
                <th class="symbol">&lt;R&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">x0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">xxxx1</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">xxx10</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">xx100</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">x1000</td>
                <td class="symbol">X</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;n&gt;</td><td><a id="sa_n"/>
        
          <p class="aml">Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="ins_advsimd_gen.html">INS (general)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1:</p>
    <ul>
      <li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
      <li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
    </ul>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
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      This document is Non-Confidential.
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